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SPECIAL FEATURE

6 Engineers’ Guide to PCI Express Solutions 2011

With the final PCIe 3.0 specification due in November 2010, tool,

board and chip vendors are working hard to conquer the new

spec’s complexities in order to take advantage of its performance

enhancements. John Wiedemeier, product marketing manager

at LeCroy; Alex Goldhammer, strategic marketing manager for

PCIe and Aurora at Xilinx; and Patrick Dietrich, hardware design

engineer at Connect Tech, discussed trends to watch and chal-

lenges to watch out for in our virtual roundtable discussion.

EECatalog: What major trends within engineering for PCI

Express are you and your colleagues spotting?

John Wiedemeier, LeCroy: There are three

protocol levels of PCI Express – Gen 1, Gen 2,

and Gen 3 – and we’re tracking each of these

separately. Even with new standards, the old

ones are still very much in force and people are

still moving towards those from other technolo-

gies. We’re still seeing

people move from PCI to

PCI Express, and we’re

still seeing embedded

applications moving away

from proprietary back-

planes to Gen 1 and Gen

2 PCI Express backplanes.

Servers are the major

adopters for PCIe 3.0;

workstations and graphics

are the major adopters for

PCIe 2.0; embedded is still moving from PCI to PCIe 1.1. People

are using the I/O technology as a differentiator against their

competition. Companies that are really sensitive to that, like

graphics cards and servers, they’ll be our first adopters for the

higher speed technology.

Patrick Dietrich, Connect Tech: We are

seeing PCI Express being used for more inter-

chip communications. A perfect example is the

new Intel Atom architecture. Normally, between

processor and chipset there is a proprietary bus.

The new architecture uses PCI Express between

processor and chipset. This is great because there is already a

robust knowledge of the specification throughout designers.

Alex Goldhammer, Xilinx: With PCI Express

Gen 2 and USB 3.0, both protocols used the

Intel PIPE 2.0 specification as the basis for the

internal interface between the Protocol Layers

and the GT (PHY). From a GT development

perspective, this should help engineering reuse

a lot of the verification and testing infrastructure needed for

transceivers. If this trend continues it will also hopefully reduce

the numbers of different transceivers in the market, making

transceivers easier to test and validate. There will always be

many, but efforts to consolidate will help.

EECatalog: What major challenges are your developers con-

fronting these days?

Wiedemeier: Dynamic equalization will be a challenge for

PCI Express Gen 3. Gen 1 and Gen 2 technologies use the same

encoding protocol, and just increased the speed and perfor-

mance characteristics.

But when they went

to Gen 3, they really

changed the protocol

drastically. One of the

ways is with dynamic

equalization. Right

now, no one has that

in place – they’re using

manual equalization

to define the lanes up

front.

Another trend that was really hyped at the Intel Developer

Forum was solid state drive (SSD) devices, and SSD debugging

will be another challenge.

Dietrich: Measuring and verifying PCI Express is becoming

more and more difficult as the bus speed increases. Generation

2 at 5 Gbps pushes the bandwidth of our current oscilloscope

and measurement equipment. With Generation 3 at 8 Gbps, our

current equipment will not be able to measure it accurately.

This will push design teams into making big investments in new

equipment.

“Measuring and verifying PCI Express

is becoming more and more difﬁcult

as the bus speed increases.”

Feel the Need for Speed?

PCI Express performance enhancements of-

fer tradeoffs for increased complexity

By Cheryl Coupé

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